The present invention relates to a semiconductor integrated circuit device and to, for example, a technique effectively applied to a shared-method sense amplifier circuit of a dynamic random access memory (hereinafter, simply referred to as “DRAM”).
In a research of publicly known examples after the invention of the present application has been filed, the following techniques are reported as those relevant to precharge of complementary bit lines similarly to that of the invention of the present application. That is, Japanese Patent Laid-Open No. 2000-100171 (Patent Document 1) discloses a DRAM in which a precharge circuit is provided inside a shared MOSFET and an equalize MOSFET is provided outside the shared MOSFET (on a memory cell side); Japanese Patent Laid-Open No. 2000-195271 (Patent Document 2) discloses that a logic level is supplied as a precharge signal of a second precharge circuit provided in an area surrounded by a shared MOSFET and a first precharge circuit is provided outside the shared MOSFET; Japanese Patent Laid-Open No. 10-284705 (Patent Document 3) discloses a DRAM in which a precharge circuit and an equalize MOSFET provided in an area surrounded by a shared MOSFET are driven by VDD; and Japanese Patent Laid-Open No. 11-288600 (Patent Document 4) discloses that a precharge circuit and an equalize MOSFET provided in an area surrounded by a shared MOSFET are driven by an internal voltage Vint (<Vpp).